PCB Design Using Parameter Constraints

PCB design Using Parameter Constraints
Nowadays, the factors considered in PCB design are becoming more and more complex, such as clock, crosstalk, impedance, detection, manufacturing technology, etc, This usually causes the designer to repeat a lot of layout, verifICation and maintenance work The Parametric Constraint Editor can specify these parameters to help designers better handle these sometimes opposite parameters in the design and production process In recent years, PCB layout and wiring have become more and more complex according to the requirements of. The number of transistors in integrated circuits is still growing at the rate predicted by Moore's Law, which makes the equipment faster and the rise time of each pulse edge shorter At the same time, the number of pins will also be increased More and more, usually 5.00 to 2000 pins All of these can cause density, timing, and crosstalk problems when designing PCBs A few years ago, most PCB boards had only a few "critical" nodes (nets), usually referring to some constraints, lengths, and gaps in impedance PCB designers usually perform these traces first Manual wiring, and then use software to automatically route the entire circuit on a large scale Today's PCB usually has 5, 000 or more nodes, of which more than 50% are key nodes Due to the time to MARKet pressure, manual wiring can no longer be performed at this time In addition, not only the number of key nodes has been increased, but also the constraints on each node These constraints are mainly due to parameter dependency and increasingly complex design requirements For example, the distance between two traces may depend on a function of node voltage and board data The rise time of digital integrated circuit is shortened Both high and low clock speed designs have an impact Due to faster pulse generation, setting and holding times are shorter In addition, interconnect delay is an important part of the total delay in high-speed circuit design This is also very important for low speed design, etc Wait If the board of directors is bigger, some of the above problems will be easier to solve, but the current trend is just the opposite Due to interconnect delay and high-density packaging requirements, circuit boards become SMAller and smaller, resulting in high-density circuit design that must follow the miniaturization design rules The combination of shorter rise time and these miniaturization design rules makes the crosstalk noise problem more and more prominent, while the ball grid array and other high-density packages themselves will exacerbate crosstalk and other problems, such as switching noise and ground bounce
PCB board

Fixed constraints exist
The traditional way to deal with these problems is to translate electrical and process requirements into fixed constraint parameters by experience, default value, table or calculation For example, when designing a circuit, engineers can first determine the rated impedance, and then "estimate" the rated linewidth that can achieve the required impedance according to the process requirements, or use a calculation table or arithmetic program to test the interference, and then find the length constraint This method usually requires a set of empirical data to be designed as the basic criteria for evaluation, which can be used by PCB designers when using automatic placement and routing tools for design The problem with this method is that empirical data is only a general principle. Most of the time, they are correct, but sometimes they do not work or lead to wrong results Let's take the impedance measurement above as an example to see the possible errors caused by this method Impedance related factors include the dielectric efficiency of the circuit board data, the height of the copper foil, the distance from each layer to the ground/power layer, and the line width Because the first three parameters are usually determined by the production process, designers usually rely on the line width Control impedance Because the distance between each circuit layer and the ground or power layer is different, it is obviously wrong to use the same empirical data for each layer The problem is further complicated by the fact that the production process or circuit board characteristics used in the development process may change at any time Most of the time, these problems will be exposed in the prototype phase, which is usually solved by repairing the circuit board or redesigning the circuit board after finding problems This is very expensive. The repair usually introduces other problems that need further debugging. The revenue lost due to the delay in time to market is far greater than the debugging cost Almost every electronic manufacturer faces this problem. In the final analysis, the traditional PCB design software cannot meet the current actual power efficiency requirements. In this regard, it is not as SIMple as the empirical data of mechanical design
Solution: Parametric Constraints
Design software vendors are currently trying to solve this problem by adding parameters to constraints.  The advantage of this method is that it can specify mechanical specifications that fully reflect various internal electrical characteristics. As long as they are added to PCB design, design software can use this information to control automatic placement and routing tools When the subsequent production process changes, there is no need to redesign The designer can automatically change the relevant constraints by simply updating the process characteristic parameters Designers can then run a DRC (design rule check) to determine if the new process also navigates other design rules, and find out which aspects of the design should be changed to correct any errors Constraints can be input in the form of mathematical expressions, including constants, various operators, vectors, and other design constraints to provide a parametric rule driven system for designers You can even enter constraints in the form of lookup tables and store them in design files on PCB or schematic diagrams PCB route, copper foil area position and layout tool must meet the constraints generated by these conditions DRC verifies whether the whole design conforms to these constraints, including line width, spacing, and space requirements (such as area and height constraints), etc A very simple example is the rise time constraint, which is usually set to a constant of 1.5ns According to this condition, the trajectory length constraint can be obtained, that is, 580 million/ns times the rise time of 1. 5ns A slightly complex example is the element spacing, which is determined by multiplying the tangent of the detection angle by the height of the equipment, and it gives the element spacing value
Hierarchical management: A major advantage of parameter constraints is that they can be handLED hierarchically For example, global lineweight rules can be used as design constraints throughout the design Of course, some regions or nodes cannot replicate this principle At this point, you can use the lower level constraints in hierarchical design around the high level constraints
1) Design constraints for all objects without other constraints.
2) Hierarchical constraints for objects on a certain layer.
3) Node type constraints for all nodes contained in a certain type.
4) Node constraints, used for a node
5) Inter class constraints, indicating the constraints between two nodes
6) Space constraints for all devices in a space.
7) Device constraints for specific devices
Example 1: Line width=f (impedance, layer spacing, dielectric constant, copper foil height)
Here is an example of how parametric constraints can be used as design rules to control impedance.  As previously mentioned, impedance is a function of dielectric constant, distance to near circuit layer, width and height of copper wire Since the impedance required for design has been determined, these four parameters can be used as any related variable to rewrite the impedance formula. In most cases, the only parameter that the designer can control is the line width Because of this, the linewidth constraint is a function of impedance, dielectric constant, distance to the near line layer, and copper foil height If the formula is defined as level constraint and the manufacturing process parameters are defined as design level constraint, the software will automatically adjust the line width to compensate when the designed line layer changes With the same pipe, if the designed circuit board is produced by another process and the copper foil height changes, as long as the copper foil height parameter is changed in the design level, the relevant rules in the level will be automatically recalculated
Example 2: Device interval = max(default interval, f(device height, detection angle)
The obvious benefit of using both parametric constraints and design rule checking is that the parametric approach is very portable and monitorable when the design is modified.  This example shows how equipment spacing is determined by process characteristics and test requirements The above formula shows that the device spacing is a function of the device height and the inspection angle Generally, the detection angle of the whole circuit board is constant, which can be defined at the design level When the check is changed to another machine, the entire design can be updated by simply entering a new value at the design level After entering the new machine performance parameters, the designer can simply run DRC to check whether the equipment spacing conflicts with the new spacing value, so as to know whether the design is feasible, rather than analysis and correction. Then a new spacing is needed to make hard calculation easier
Example 3: Component Layout
In addition to organizing design objects and constraints, design rules can also be used for component placement, which means that it can detect the placement position of equipment according to constraints without introducing errors The highlighted part in Figure 1 is the device placement area that meets physical constraints (such as spacing from board edges and device spacing, etc.) In fact, modular pipeline generation can greatly improve its maintainability and reusability By referring to the constraint parameters of different layers in the previous stage, new expressions can be generated. For example, the top layer line width depends on the top layer distance and copper wire height, as well as the variables Temp and Diesel Const in the design level Note that design rules are displayed in ascending order, and changing the high constraint will immediately affect all expressions that reference the constraint
Design reuse and archives
Not only can parameter constraints significantly improve the initial design process, but they are also more useful for engineering change and design reuse Constraints can be part of the design, system, and documentation. If it is not the idea of engineers or designers, then when they move to other projects, they may slowly forget The constraint file records the power efficiency rules that should be followed in the design process, and provides an opportunity for others to understand the designer's intent so that these rules can be easily applied to new manufacturing processes or changed according to power efficiency requirements Future reusers can also know the exact design rules and change them by inputting new process requirements without having to guess how to obtain line width Parametric constraint editor is helpful for the layout and routing of PCB boards under multiple constraints. Once again, it enables automatic routing software and design rules to conduct a comprehensive inspection according to complex power and process requirements, rather than just experience or simple, useless design rules The result is a successful PCB board that reduces or even eliminates prototype design